1. Field of the Invention
The present invention relates to a process for forming conductive regions such as wiring lines and for filling the gaps between conductive regions in a semiconductor circuit with a dielectric material using high density plasma chemical vapor deposition.
2. Description of the Prior Art
Many highly integrated semiconductor circuits utilize multilevel wiring line structures for interconnecting regions within devices and for interconnecting one or more devices within the integrated circuits. In forming such structures, it is conventional to provide first or lower level wiring lines or interconnect structures and then to form a second level wiring line in contact with the first level wiring lines or interconnect structures. A first level interconnect might be formed in contact with a doped region within the substrate of an integrated circuit device. Alternately, a first level interconnect might be formed to a polysilicon or metal wiring line that is in contact with one or more device structures in or on the substrate of the integrated circuit device. One or more interconnections are typically formed between the first level wiring line or interconnect and other portions of the integrated circuit device or to structures external to the integrated circuit device. This is accomplished, in part, through the second level of wiring lines.
Most often, the wiring lines of the multilevel interconnect structure are formed by conventional photolithographic techniques. For example, devices such as FETs, diodes or transistors are formed in and on the substrate to form an integrated circuit device and a first level of insulating material is deposited over the device. A pattern of contact holes is defined through the first level of insulating material and, at some point in the process, the contact holes are filled with a conducting material to define vertical interconnects through the first level of insulating material to contact points of the appropriate ones of the devices on the surface of the substrate. A first metal layer that will be patterned to form a first level of wiring lines is provided on the first level of insulating material and over the surface of the device. An etch mask is formed on the surface of the first metal layer that defines a pattern of wiring lines to connect to various ones of the vertical interconnects. Generally, the etch mask is formed by providing a layer of photoresist on the surface of the first metal layer, exposing the layer of photoresist through an exposure mask and developing the photoresist to form the etch mask. Etching processes remove those portions of the first metal layer exposed by the etch mask, leaving behind the desired pattern of wiring lines.
Reduced design rules for forming integrated circuit devices have necessitated the use of photolithography steppers that use short wavelength exposure sources. Such short wavelength exposure sources allow for finer resolution lithography, but have the drawback of much higher levels of reflection from different components of the integrated circuit device. For example, during exposure of the photoresist mask, it is possible that light may pass entirely through the photoresist and reflect from the surface of the first metal layer back into the lower portions of the photoresist layer. To the extent that the reflected light is scattered by the surface of the first metal layer, it is possible that unwanted portions of the photoresist layer might be exposed. These unwanted reflections could undesirably narrow the first level metal wiring lines formed in this process.
It is desirable for the wiring lines and gaps between the wiring lines to be formed as accurately as possible. Misalignment or improper thickness of the developed photoresist protective layer may cause light to be reflected from the surface of a metal layer back up to the photoresist layer, exposing portions of the photoresist layer that are intended to not be exposed. Such additional exposure from light reflecting from the underlying metal layer may cause the developed portion of the photoresist layer to have a larger width than intended, which means that a narrower than intended surface area will be etched and the wiring lines may be too close together, leading to undesirable capacitive coupling or even shorting between lines. In addition, light reflected from the underlying metal layer may cause portions of the photoresist layer to be thinner than intended, which may result in the thinner portions being etched through and the underlying metal layer, which should be protected by the photoresist, will be partially etched. Such partial etching may form voids in the wiring lines and lead to decreased device performance and/or failure. The use of photoresist masks can also lead to contamination from the photoresist, such as carbon compounds, being deposited in the gaps between wiring lines or on the wiring lines and forming defects that interfere with processing and ultimately hinder device performance.
As devices are scaled to smaller geometries, the gaps formed between wiring lines generally have high aspect ratios (ratio of height to width) which are harder to fill with dielectric material than small aspect ratio gaps. In addition, as the distance between wiring lines and other conductors becomes smaller, capacitive coupling between wiring lines and other conductors becomes a limitation on the speed of the integrated circuit device. For adequate device performance in reduced dimension devices, it is necessary that the lithography and etching steps be accurately carried out to ensure proper location and sizing of the wiring lines and gaps. It is also necessary that the dielectric material subsequently deposited into the gaps between wiring lines meet a number of requirements. The dielectric material should be able to completely fill the gap between conductors and should be planarizable so that successive layers can be deposited and processed. The dielectric material should also be resistant to moisture transport and have a predictable and low dielectric constant to minimize capacitance between adjacent wiring lines and between wiring lines on different layers.
It is thus important to accurately form the wiring lines and gaps, and to deposit a high quality, substantially void-free dielectric into the gaps. Dielectric layers for wiring line isolation are often formed by chemical vapor deposition (CVD) processes, which deposit material onto a surface by transporting certain gaseous precursors to the surface and causing the precursors to react at the surface. Common CVD methods include atmospheric-pressure CVD (APCVD), low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD). High quality APCVD and LPCVD oxides may be deposited at high temperatures (650-850° C.), but such temperatures are generally not compatible with preferred wiring materials such as aluminum. Lower temperature APCVD and LPCVD processes tend to yield oxides that are comparatively more porous and water absorbing and that may be poorly suited to use as intermetal dielectrics. Acceptable oxides may be formed using PECVD processes, which use a plasma to impart additional energy to the reactant gases. The additional energy supplied by the plasma enables PECVD processes to be carried out at lower temperatures (approximately 400° C. and less) than APCVD or LPCVD processes.
One known method for depositing dielectric material between wiring lines forms a sandwich of a layer of silane-based or TEOS-based oxide deposited by PECVD together with a layer of spin-on-glass provided in the gaps and over the wiring lines. Another method deposits only a TEOS-based dielectric layer into the gaps and over the wiring lines. Problems relating to moisture absorption, spin-on-glass outgassing and incomplete gap fill in small geometries are observed and are likely to become more problematic for further reductions in device size. Thus, it would be desirable to provide a method for filling small geometry, high aspect-ratio gaps with a dense, high quality dielectric material.